The present invention relates generally to semiconductor devices and, more particularly, to an apparatus and method for regulating electrical fuse programming current in semiconductor devices.
Electrically programmable fuses (eFUSEs) or electrical fuses are widely used to implement memory redundancy functionality in dynamic random access memory (DRAM), static random access memory (SRAM) and embedded memory devices. Programmable fuses can also be utilized in applications such as electronic chip identification, product feature personalization, and thermal diode calibration, to name a few. In a redundancy application, for example, chips returned from fabrication are usually tested and a certain percentage of them are usually found to be bad (e.g., from random contingencies that may occur in the fabrication process). The percentage of good, usable chips is commonly referred to as the “yield.” Accordingly, redundancy may enable programming a chip at the testing phase so that flawed portions of the chip are not used in favor of unflawed redundant portions, thereby increasing the yield and decreasing the percentage of chips that must be thrown away as unusable. Many of the applications for electrical fuses combine the electrical fuse with the use of a memory in some way, for example, as part of a memory cell.
Additionally, in electronic chip identification or part number identification, an eFUSE may be used to “program” or write information into a non-volatile memory, which may be comprised of individual memory cells, and the information can then be read from the memory as a unique chip identifier or part number identifier. Furthermore, for thermal diode calibration, a non-volatile memory programmed using electronic fuses can be used to hold a test temperature and the thermal diode voltage read at the test temperature.
Regardless of the specific application environment, an eFUSE is typically programmed by passing a sufficient current through the structure such that its resistance is significantly altered from its initially fabricated state. In order to determine whether a particular fuse has been programmed or not, a sense circuit may be used to detect one of two possible “states” of the fuse. More specifically, the sense circuit holds one of two latched values therein, which is driven by a comparison between a fuse voltage generated in response to a current directed through the fuse, by the sense circuit, and a reference voltage generated within the sense circuit. The reference voltage is designed to be between a fuse voltage corresponding to the programmed state and a fuse voltage corresponding to the unprogrammed state.
To achieve consistent operation and desired yields for electrical fuse programming, an accurate programming current is required. If the programming current is too low, insufficient power is coupled into the fuse to shift its resistance to a required level for sensing the blown state. If the programming current is too high, the fuses can rupture, causing reliability fails as well as the potential for “healing” over time (e.g., the “programmed” can decrease to the unprogrammed resistance over time). To avoid these problems, a controlled programming current is desired which is consistent from lot to lot.
A conventional eFUSE programming current scheme is illustrated in FIG. 1, in which a circuit path 100 includes a PFET programming transistor (P0) that supplies current to a bitline (BL) 102 connected to a group of fuse bitcells 104. A given select line (e.g., RSEL_0, RSEL_1, etc.) enables a selected bitcell 104 for programming by turning on an NFET 106 placed in series with a fuse (e.g., polysilicon) 108. The programming voltage source (FSOURCE) used to supply the fuse programming current is at a higher voltage with respect to the nominal VDD supply rail of the chip logic devices. For example, if VDD is 1.0 volt, then FSOURCE may be about 1.5-1.7 volts. To determine the state of a given fuse on an output FOUT, the bitline 102 is also coupled to a sense amplifier 110 as known in the art.
Ideally, the target programming current for each selected fuse is typically on the order of about 7-10 milliamps (ma), with the best programming conditions occurring within a narrow current range. However, across a full process window, the FET device current variance is about ±17% at a single gate voltage. Additionally, the full rail gate voltage (i.e., VDD-GND) cannot be controlled to better than about 100 millivolts (mV) of tolerance, which causes additional error in the programming current. Such variability causes insufficient programming current for weak devices and/or too much programming current for strong devices across the process window.
There are a few known solutions to this problem, all of which have drawbacks associated therewith. For example, one solution is to adjust the programming condition to the circuit depending on parametric data taken from the chip. This data would include, for example FET device Id_sat (saturation current) and parametrics for the device type used to program the fuse. Using this information, the applied conditions can be tailored to optimize yield on a chip-by-chip or wafer-by-wafer basis. However, this method is time consuming and very expensive to implement in a manufacturing environment. Another solution is to use redundant fuses or error correction (ECC) on the fuses to improve device yield. This method can still have issues with ruptured fuse reliability and suffers from area loss due to the redundant fuses and ECC circuits. Still another solution is to try to provide the programming current directly from a tester. This is difficult to implement since programming current is switched to a selected fuse, and although a tester can supply an accurate steady state current, a switched current will have high voltage compliance ranges and require a settling time from interaction with pin inductance. L di/dt will create unknown voltage spikes and complicate programming.
Accordingly, it would be desirable to be able to provide accurate fuse programming current for consistent fuse blow operation with minimal test overhead.